1. Field of the Invention
The present invention is directed to an improvement a soft error resistance property of a CMOS (Complementary Metal Oxide Semiconductor) static RAM Random Access Memory), and more particularly relates to a semiconductor memory device capable of avoiding a problem with fatal multi-bit errors.
2. Description of the Background Art
FIG. 14 is an equivalent circuit diagram of a general SRAM memory cell and shows two-bit memory cells MC0 and MC1 arranged adjacent to each other in a row direction. In reference to FIG. 14, first, memory cell MC0, as a one-bit memory cell circuit, will be described. Memory cell MC0 has two driver transistors N1A and N2A, two access transistors N3A and N4A, and two load transistors P1A and P2A. Two driver transistors N1A and N2A and two access transistors N3A and N4A are formed of nMOS transistors while two load transistors P1A and P2A are formed of pMOS transistors.
A first inverter is formed of nMOS transistor N1A and pMOS transistor P1A while a second inverter is formed of nMOS transistor N2A and pMOS transistor P2A. One output terminal of the first and second inverters are connected to another input terminals of the second and first inverters, respectively, thereby storage nodes ma and /ma are formed.
A source, a gate and a drain of nMOS transistor N3A are connected to one memory terminal ma, a word line WL and one bit line BLA, respectively. A source, a gate and a drain of nMOS transistor N4A are connected to the other memory terminal/ma, word line WL and the other bit line/BLA, respectively.
With the above described connection, the SRAM memory cell circuit is formed. Memory cell MC1 also has approximately the same configuration as that of the above described memory cell MC0.
Then, respective gates of respective access transistors N3A, N4A, N3B and N4B of the plurality of memory cells MC0 and MC1, which are aligned in the same row, are connected to common word line WL. Thereby, the memory cells aligned in the same row are simultaneously accessed when word line WL is risen.
A plan view layout configuration of such an SRAM memory cell is disclosed in, for example, Japanese Patent Laying-Open No. 9-270468.
FIG. 15 is a schematic plan view showing a layout configuration of the conventional SRAM memory cell shown in the above described publication using two-bit memory cells MC0 and MC1 arranged adjacent to each other in the row direction. In reference to FIG. 15, each of memory cells MC0 and MC1 is formed on surfaces of an n-type well 102 and of a p-type well 103 formed on a surface of a semiconductor substrate. According to description of memory cell MC0, two nMOS transistors N1A and N2A, which become a pair of driver transistors, and two nMOS transistors N3A and N4A, which become a pair of access transistors, are formed within p-type well 103. Two pMOS transistors P1A and P2A, which become a pair of load transistors, are formed within n-type well 102.
Driver transistors N1A and N2A have drains formed of n-type impurity regions 105a2, sources formed of n-type impurity regions 105a3 and gates 107c and 107b extending onto the regions between these drains and sources, respectively. Access transistors N3A and N4A have drains formed of n-type impurity regions 105a1, sources formed of n-type impurity regions 105a2 and gates 107a extending onto the regions between these drains and sources, respectively.
Source 105a2 of access transistor N3A and drain 105a2 of driver transistor N1A are formed of a common n-type impurity region. In addition, source 105a2 of access transistor N4A and drain 105a2 of driver transistor N2A are formed of a common n-type impurity region. Respective gates 105a of access transistors N3A and N4A are integrated with a single word line.
Load transistors P1A and P2A are formed of drains formed of p-type impurity regions 105b1, sources formed of p-type impurity regions 105b2 and gates 107c and 107b extending onto the regions between these drains and sources, respectively. Gate 107c of load transistor P1A and gate 107c of driver transistor N1A are formed of the common conductive layer while gate 107b of load transistor P2A and gate 107b of driver transistor N2A are formed of the common conductive layer.
Drain 105a2 of driver transistor N2A, drain 105b1 of load transistor P2A and respective gates 107c of load transistor P1A and driver transistor N1A are electrically connected by means of a conductive layer 112. Drain 105a2 of driver transistor N1A, drain 105b1 of load transistor P1A and respective gates 107b of load transistor P2A and driver transistor N2A are electrically connected by means of a conductive layer 112.
In addition, conductive layer 112 which is electrically connected to source 105a3 of driver transistor N2A and conductive layer 112 which is electrically connected to source 105a3 of driver transistor N1A are electrically connected by means of a conductive layer 114 serving as a GND potential. In addition, both source 105b2 of load transistor P1A and source 105b2 of load transistor P2A are electrically connected to conductive layer 114 serving as a VDD potential. In addition, drain 105a1 of access transistor N3A is electrically connected to bit line BL while drain 105a1 of access transistors N4A is electrically connected to bit line/BL.
Memory cell MC1 has approximately the same configuration as that of the above described memory cell MC0.
Driver transistors N1A and N2A and access transistors N3A and N4A of this memory cell MC0 as well as driver transistors N1B and N2B and access transistors N3B and N4B of memory cell MC1 are formed within common p-type well 103. In addition, respective drains 105b1 and respective sources 105b2 of load transistors P1A and P2A of memory cell MC0 as well as respective drains 105b1 and respective sources 105b2 of load transistors P1B and P2B of memory cell MC1 are formed within common n-type well 102.
As the memory cells are miniaturized, a problem with a soft error, that data hold in a storage node is inverted due to electrons generated by xcex1 rays emitted from a package or due to neutron rays from space, becomes evident. In particular, this malfunction becomes evident as the power supply voltage is lowered.
One of the causes that invert the data hold in a storage node is the collection of a large number of electron hole pairs generated within a well by xcex1 rays or neutron rays in an impurity region forming a storage node, changing the potential thereof. Electrons from among electron hole pairs generated within a p-type well are collected in an n-type impurity region within the same p-type well, thereby the potential of this n-type impurity region tends be lowered. In addition, holes among electron hole pairs generated within an n-type well are collected in a p-type impurity region within the same n-type well, thereby the potential of this p-type impurity region tends be raised. In the case that this p-type impurity region or n-type impurity region is a memory node, a so-called soft error generates, which the hold data is inverted by change in potential due to the collected electrons or holes.
In order to avoid the above described problem with soft errors, a variety of measures such that a capacitor is attached to a memory node so as to make it difficult to be inverted have been carried out up to the present. However, as miniaturization has progressed, the lowering of voltage has progressed and the capacitance of a memory node has become increasingly smaller. Therefore, circumstances have become such that an increase in area in order to attach a capacitor so as to prevent inversion cannot be avoided. For example, the capacitance of a memory node of an SRAM memory cell in the 0.18 xcexcm generation is approximately 2 fF so that the amount of charge collected in a memory node due to the application of one shot of xcex1 rays is as large as approximately several fC. Therefore, in the case that the power supply voltage is 1.8 V, electron hole pairs sufficient for generating a capacitance corresponding to 10 fF are generated. Thereby, it is understood that the data of the memory node is easily inverted. In addition, the number of electron hole pairs generated by the application of neutrons is ten times or more that from the application of xcex1 rays and, therefore, the addition of a slight amount of capacitance is no longer said to be effective for neutron rays.
A soft error has become a problem as described above and, on the other hand, a measure for nullification of the effect on the entire system, even in the case that a soft effort is generated, has been implemented by adding an error correction circuit (ECC circuit). Normally, the general case is wherein a redundancy code is added so that two-bit error detection and one-bit error correction are possible. Circuit configuration becomes very complicated when an error correction of more than that is attempted to be carried out and this is undesirable because circuit scale is significantly increased.
In the case that this ECC circuit for allowing one-bit error correction is provided, a one-bit soft error is automatically corrected when it generates and, therefore, the system is not affected. In the case that an error of two bits or more has generated, however, system reset is triggered when the generation of a two-bit error is detected. In a case where a multi-bit error has generated in such a manner, there is a problem that error correction becomes difficult so that it becomes a fatal error for the entirety of the system.
In the conventional memory cell configuration shown in FIG. 15, n-type well 102 and p-type well 103 are shared between memory cells adjoining each other. As miniaturization progresses, the distance between respective bits is reduced so that electron hole pairs generated within a well due to xcex1 rays or neutron rays are collected in impurity regions of a plurality of bit cells arranged adjacent to each other, thereby the possibility of simultaneously causing errors has increased. In particular, electrons have a higher mobility in comparison with holes and, therefore, exert a greater influence than do holes. Thus, in the case that the two-bit data arranged adjacent to each other is inverted due to a soft error and the data is simultaneously accessed, a problem arises, which the above described multi-bit error is generated and this becomes a fatal error for the entirety of the system.
An object of the present invention is to provide a semiconductor memory device capable of preventing generation of a multi-bit error.
A semiconductor memory device of the present invention is a semiconductor memory device which has a memory cell array including a plurality of memory cells arranged in a row direction and in a column direction and which is provided with a semiconductor substrate, a first conductive type region and a second conductive type region, and first and second word lines. The semiconductor substrate has a main surface. The first conductive type region and the second conductive type region extend in the column direction while arranged adjacent to each other in the main surface of the semiconductor substrate. The first and second word lines are arranged in the plurality of rows, respectively. Each of first and second memory cells arranged adjacent to each other among the plurality of memory cells arranged so as to be aligned in the same row has first and second access transistors. The first and second access transistors of the first memory cell and the first and second access transistors of the second memory cell are formed within the same first conductive type region. Each gate of the first and second access transistors of the first memory cell is electrically connected to the first word line while each gate of the first and second access transistors of the second memory cell is electrically connected to the second word line.
According to the semiconductor memory device of the present invention, since the access transistor of the first memory cell and the access transistor of the second memory cell are connected to different word lines, it is possible to make the first and second word lines to be simultaneously risen by corresponding the first and second word lines to different addresses. Thereby, two-bit memory cells, which are arranged adjacent to each other, sharing a region of the first conductive type can be prevented from being simultaneously accessed, thereby the generation of a multi-bit error can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.